DMA FIXES IN AG71XX ETHERNET DRIVER
As the Raspberry Pi is an inexpensive piece of hardware and intended for educational use, the Xinu operating system, which is simple and intended for educational use, will be a very good fit for it. Finally, in the afternoon Dr. Soylent Green Is People! I found that Bulk transfers behaved slightly differently from how I expected because the Host Controller sometimes transferred more than one packet before halting the channel. But if, hypothetically, the ARM was indeed using the L1 data cache, then this could in principle cause DMA to not work correctly due to cache coherency not being maintained; after all, the L1 data cache is apparently internal to the ARM processor, and other devices located on the system AMBA bus are not aware of it. The remaining talks were in the morning.
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I am currently just using “ping” with various packet sizes and intervals, since there is little reason to test more advanced networking functionality such as TCP until ping is fully functional ag1xx no apparent bugs, regardless of the packet load.
Our next task will probably be to better integrate our work into the existing Embedded Xinu codebase rather than using a separate source tree. As Xinu is supposed to be meant for education, I re-wrote erhernet function to be as simple as possible, halving the lines of code excluding the detailed comments I added. However, I haven’t yet been able to verify that this feature is actually being used by the hardware and is working correctly.
In doing this I fixed and improved the Doxygen-compatible comments in various files, and I am also considering using Doxygen groups so that one can, for example, easily browse to the documentation for all external functions included in Xinu’s C library, the UART driver, or any other module, rather than browsing file-by-file.
In the morning I attempted to figure out why the “kexec” command I programmed was not working. Therefore, we must use the Linux source code as a substitute for the nonexistent documentation. However, these had no noticeable effect on our existing code.
Implementing control transfers in this way actually reduced the code size and arguably simplified the code because then all the code that performed synchronous transfers could be deleted, thereby sending all transfers on the same code path. The Linux kernel uses 0xbased addresses, whereas our code previously used 0-based addresses.
Begin writing network bootloader. Therefore I’m planning to give an extended and updated version of the talk I gave at the end of June. The RTL is the router switch in these units. This might become clear once we are successfully able to enumerate the devices attached to this hub, which we have the code to do, but it is not working yet, probably due to problems with the control transfers.
Brylow expressed frustration with the lack of good quality documentation about current and past hardware.
He thought that especially after the sections I had written about various aspects such as interrupts, USB, Ethernet, and the system timer, we’re on track to submit the paper. This page has been accessed dam, times. There should be 2 sets of hex. Based on this, I was able to begin implementing additional required functions, such as etherControl, etherReadand etherWrite.
# (update ar71xx/arx ethernet dma stuck patch from openwrt) – DD-WRT
The device has a bulk-in endpoint for ethernet reception and a bulk-out endpoint for ethernet transmission. But obviously networking does not actually work yet as the ethernet driver routines need to be filled ethrenet with actual implementations. The USB standard has many pages detailing the scheduling rules for such transactions. It’s stated to be “L2 cache coherent non-allocating “.
RX AssocResp from Our initial work will consist of getting basic functionality working, including the UART, interrupts, and system timer. The table we implemented two days ago contained ARM instructions that jumped to the exception handler entry points using relative offsets.
Luckily, there was a brief overview of the USB ethernett, which gives some of the basic information that we need. CFI does not contain boot bank location.
We can therefore conclude that the ARM code running on Xinu up until this point uses neither the L1 or L2 caches for data. This is the preliminary to get interrupt-driven bulk transfers at71xx work, which are required by any sane cma of the ethernet driver otherwise there is no way for the system to be actually notified when an Ethernet packet is received.
[source] ar71xx: prevent spurious ethernet resets from dma hang check false positives
On the weekend I spent some time improving the USB Host Controller ethernef, including documenting the registers that it uses and implementing support for asynchronous, interrupt-driven control transfers. Shared normal memory is cache-coherent, so one might expect that we would need to use this type of memory for DMA. I will work on the former, since Tyler wanted to write the HID keyboard driver. The other test failures we will investigate later this week.
Secondly, some patches did not apply correctly due to SVN unhelpfully changing the contents of files by itself via the magical SVN tags “feature”.